DESIGN AND ANALYSIS OF ASYNCHRONOUS ADDERS

An asynchronous adder can take advantage of the shorter carry propagat ion chains that occur in practice and exhibit a data-dependent computa tion delay. Basically, an asynchronous adder has a mechanism to announ ce early completion by detecting when it is done. Such an adder is ext remely useful in asynchronous implementation of computing structures. In this paper we evaluate the designs tradeoffs of well-known asynchro nous adder configurations based on ripple-carry and carry lookahead to pologies. We show that, using complex gates, carry lookahead asynchron ous adders can be realised that outperform ripple-carry asynchronous a dders, both in average-case delay and worst-case delay without increas ing the area and power consumption. The underlying timing assumptions and applications of the adder in asynchronous pipelines (micropipeline s) are also discussed.