LOGIC SYNTHESIS FOR A FINE-GRAIN FPGA

The paper describes an algorithm which combines logic synthesis and te chnology mapping specifically for Xilinx's XC6200, a new family of fin e-grain, dynamically reconfigurable FPGA. The algorithm employs a BDD representation of the logic function and a genetic algorithm (GA) is u sed to find a good decomposition variable ordering. The algorithm also exploits the architectural features of the XC6200 to minimise the num ber of cells required to implement a given function. Results on benchm ark circuits show that the new algorithm performs similarly or better than other synthesis tools in a large number of cases.