MAXIMUM POWER ESTIMATION FOR CMOS CIRCUITS USING DETERMINISTIC AND STATISTICAL APPROACHES

Excessive instantaneous power consumption may reduce the reliability a nd performance of VLSI chips, Hence, to synthesize circuits with high reliability, it is imperative to efficiently obtain a precise estimati on of the maximum power dissipation, However, due to the inherent inpu t-pattern dependence of the problem, it is impractical to conduct an e xhaustive search for circuits with a large number of primary inputs, H ence, the practical approach is to generate a tight lower bound and an upper bound for maximum power dissipation within a reasonable amount of central processing unit (CPU) time, In this paper, instead of using the traditional simulation-based techniques, we propose a novel appro ach to obtain a lower bound of the maximum power consumption using aut omatic test generation (ATG) technique. Experiments with MCNC and ISCA S-85 benchmark circuits show that our approach generates the lower bou nd with the quality which cannot be achieved using simulation-based te chniques, In addition, a Monte Carlo-based technique to estimate maxim um power dissipation is described, It not only serves as a comparison version for our ATG approach, but also generates a metric to measure t he quality of a lower bound from a statistical point of view.