BEHAVIORAL-LEVEL SYNTHESIS OF HETEROGENEOUS BISR RECONFIGURABLE ASICS

In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, including 1) design for f ault tolerance against permanent faults, 2) design for improved manufa cturability, and 3) design of application specific programmable proces sors (ASPP's)-processors designed to perform any computation from a sp ecified set on a single implementation platform, This paper focuses on design techniques for efficient built-in self-repair (BISR), and thus directly addresses the former two applications. Previous BISR techniq ues have been based on replacing a failed module with a backup of the same type, We present new heterogeneous BISR methodologies which remov e this constraint and enable replacement of a module with a spare of a different type. The approach is based on the flexibility of behaviora l-level synthesis to explore the design space, Two behavioral synthesi s techniques are developed; the first method is through assignment and scheduling, and the second utilizes transformations. Experimental res ults verify the effectiveness of the approaches.