A NOVEL DESIGN OF A 2 OPERAND NORMALIZATION CIRCUIT

This paper presents a new design for two operand normalization. The tw o operand normalization operation involves the normalization of at lea st one of two operands by left shifting both by the same amount, Our d esign performs the computation of the shift by making an OR of the bit s of both operands in a tree network, encoding the position of the fir st nonzero bit. The encoded position is obtained most significant bit first, and then there is an overlapping with the shifting operation, T he design we propose replaces two leading zero detector circuits and a comparator, that are present in the conventional approach, Our scheme demonstrates to be more area efficient than the conventional one, The circuit we propose is useful in floating point complex multiplication and COordinate Rotation DIgital Computer (CORDIC) processors.