THE PHYSICAL AND ELECTRICAL EFFECTS OF METAL-FILL PATTERNING PRACTICES FOR OXIDE CHEMICAL-MECHANICAL POLISHING PROCESSES

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance, Metal-fill patterning pra ctices have emerged as a technique for substantially reducing layout p attern dependent no thickness variation, We present a generalizable me thodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specifi cation while minimizing the added interconnect capacitance associated with metal-fill patterning, Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickne ss variation, a 20% improvement in uniformity in one case and a 60% im provement in the other case, and illustrate that pattern density is th e key mechanism involved, The pros and cons of two different metal-fil l patterning practices-grounded versus floating metal-are explored, Cr iteria for minimizing the effect of floating or grounded metal-fill pa tterns on delay or crosstalk parameters are also developed based on ca nonical metal-fill structures. Finally, this methodology is illustrate d using a case study which demonstrates an 82% reduction in ILD thickn ess variation.