A PROPOSED CMOS BUFFER FOR LOW-VOLTAGE ENVIRONMENTS

This article presents a novel CMOS buffer, based on utilizing the para sitic bipolar transistor, associated with the pMOS device, to enhance the circuit speed. The proposed configuration is particularly suitable for the submicron regime and its circuit performance improves substan tially with scaling the technology. The new circuit was analyzed and H SPICE simulations were performed for three submicron technologies. The performance evaluation has shown that for the same input capacitance, the new circuit outperforms the conventional buffer in terms of speed . A figure-of-merit of the new circuit, based on the propagation delay , power dissipation and chip area, is also computed. (C) 1998 Elsevier Science Ltd.