PLANARIZED MULTILEVEL INTERCONNECTION USING CHEMICAL-MECHANICAL POLISHING OF SELECTIVE CVD-AL VIA PLUGS

A planarization process for selective CVD-AI via plugs using chemical mechanical polishing (CMP) is proposed and a four-level interconnectio n system with all stacked via plugs is demonstrated, A Cl-2/Ar post-cl eaning treatment after Al plug CMP is shown to be the key process in o btaining excellent via chain characteristics with high yield and small resistance scattering, A sandwich of Ti/TiN/Ti barrier layers with a CVD-AI plug is proved to be one of the best via plug structures becaus e of its low via resistance and high reliability, Quarter-micron 120-k G gate array LSI's have been successfully fabricated using a 1.3-mu m, equal pitch and four-level interconnection.