With reference to the mainstream technology, the most relevant failure
mechanisms which affect yield and reliability of Flash memory are rev
iewed, showing the primary role played by tunnel oxide defects. The ef
fectiveness of a good test methodology combined with a proper product
design for screening at wafer sort latent defects of tunnel oxide is h
ighlighted as a key factor for improving Flash memory reliability. The
degradation of device performance induced by program/erase cycling is
discussed, covering both the behaviour of a typical cell and the evol
ution of memory array distribution. The erratic erasure phenomenon is
illustrated as the most relevant mechanism reported so far to cause si
ngle bit failures in endurance tests. Finally, reliability implication
s of multilevel cell concepts are briefly analysed. (C) 1998 Elsevier
Science Ltd.