STI PROCESS STEPS FOR SUB-QUARTER MICRON CMOS

This paper presents Shallow Trench Isolation (STI) process steps for s ub-1/4 mu m CMOS technologies. Dummy active areas, vertical trench sid ewalls, excellent gap filling, counter mask etch step and CMP end poin t detection, have been used for a 0.18 mu m CMOS technology. Electrica l results obtained with a 5.5 nm gate oxide thickness show good isolat ion down to 0.3 mu m spacing. Good transistor performances have been d emonstrated. (C) 1998 Published by Elsevier Science Ltd.