DESIGNS FOR SELF-CHECKING FLIP-FLOPS

Citation
Sm. Kia et S. Parameswaran, DESIGNS FOR SELF-CHECKING FLIP-FLOPS, IEE proceedings. Computers and digital techniques, 145(2), 1998, pp. 81-88
Citations number
13
Categorie Soggetti
Computer Science Hardware & Architecture","Computer Science Theory & Methods","Computer Science Hardware & Architecture","Computer Science Theory & Methods
ISSN journal
13502387
Volume
145
Issue
2
Year of publication
1998
Pages
81 - 88
Database
ISI
SICI code
1350-2387(1998)145:2<81:DFSF>2.0.ZU;2-K
Abstract
The authors introduce two low-cost. modular, totally self checking (TS C), edge triggered and error propagating (code disjoint) flip-flops. o ne, a D flip-flop used in TSC and strongly fault secure (SFS) synchron ous circuits with two-rail codes, the other a T flip-flop, used in a s imilar way as the D flip-flop but retaining the error as an indicator until the next presetting, to aid error propagation. Thus, the self ch ecking T flip-flop can be used as an error indicator. The self checkin g D flip-flop is smaller than the duplicate D flip-flop circuitry by 3 0%. The self checking T flip-flop error indicator is 60% smaller than the pervious error indicator in the literature. These circuits, unlike previously reported circuits, can also detect stuck-at faults in the clock inputs. The authors have also presented TSC/error propagating ap plications for the above flip-flops: a counter and a shift register.