DATAPATH LAYOUT OPTIMIZATION USING GENETIC ALGORITHM AND SIMULATED ANNEALING

The paper deals with the minimisation of the track density and the int erconnection delay in the design of a high-performance compact datapat h. The authors applied a hybrid approach of genetic algorithm (GA) and simulated annealing (SA) to determine the optimal datapath element or dering to minimise both the track density and the wire length. To impr ove the computation speed, they used the datapath-specific genetic ope rators. Experimental results for the 'real-world' microprocessor examp les show that the GA/SA hybrid approach outperforms the existing genet ic approaches and gives similar results to simulated annealing with mu ch less computation time.