DIGIT-SERIAL SYSTOLIC MULTIPLIER FOR FINITE-FIELDS GF(2(M))

A new digit-serial systolic array is proposed for computing multiplica tions in finite fields GF(2(m)) With the standard basis representation . If input data come in continuously the proposed array can produce mu ltiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. Each cell of the array can be further pi pelined so that the maximum propagation delay can be kept small to mai ntain a high clock rate when the digit size L gets large. The proposed architecture possesses the features of regularity, modularity, and un idirectional data flow. It is thus well suited to VLSI implementation with fault-tolerant design. As compared with existing bit-serial and b it-parallel multipliers for GF(2(m)), the proposed digit-serial archit ecture gains an advantage in terms of improving the trade-off between throughput performance and hardware complexity.