APPROACHES TO EXTRA LOW-VOLTAGE DRAM OPERATION BY SOI-DRAM

The newly designed scheme 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-v oltage/high-speed SOI-DRAM will be described here. The extra low volta ge DRAM technologies are composed of the modified MESA isolation witho ut parasitic MOS operation, the dual gate SOI-MOSFET's with tied or Bo ating bodies optimized for DRAM specific circuits, the conventional st acked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bia s control technique was applied for body-tied MOSFET's to realize high performance even at low voltage. Integrating the above technologies i n the newly designed 0.5-mu m 16 MDRAM, high-speed DRAM operation of l ess than 50 ns has been obtained at low supply voltage of 1 V.