ADVANCED TECHNOLOGIES FOR OPTIMIZED SUB-QUARTER-MICROMETER SOI CMOS DEVICES

Two manufacturable technologies of fully-depleted (FD) thin-film silic on-on-insulator (SOT) MOSFET's for low-power applications are proposed in this paper, To maintain high current drive while aggressively thin ning down the SOI film, silicide is to be formed on Ge-damaged silicon layers, Ge preamorphization facilitates silicide formation at ion tem perature (similar to 450 degrees C) and effectively controls the silic ide depth without void formation. It also reduces the floating body ef fect. In addition, a reliable gate work-function engineering is introd uced for good threshold voltage management. A p(+) SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickn ess nonuniformity and broadens the design window for channel doping. T hese advanced technologies, compatible with existing bulk CMOS technol ogy, are integrated into SOI CMOS process. Excellent electrical device results are presented.