EFFECT OF EPILAYER CHARACTERISTICS AND PROCESSING CONDITIONS ON THE THERMALLY OXIDIZED SIO2 SIC INTERFACE/

The optimization of the SiO2/SiC Interface is critical for the develop ment of SiC MOS devices. We investigate the effects of several variabl es spanning both epilayer attributes and processing conditions relativ e to our control oxidation process. Varying the shallow vicinal angle of the wafer does not affect the interface. There is a definite degrad ation of the interface as the epilayer doping density is increased. Sa crificial oxidation appears to reduce the number of border traps in th e final oxide. Fluorine annealing has no effect on the interface quali ty. A low temperature (950 degrees C) re-oxidation, which follows a bu lk oxide growth at 1150 degrees C, reduces D-it to the mid-10(10) cm(- 2)eV(-1) range near midgap and Q(f) to a record low 5 x 10(11) cm(-2).