AUTOMATED SYNTHESIS OF SKEW-BASED CLOCK DISTRIBUTION NETWORKS

In this paper a top-down methodology is presented for synthesizing clo ck distribution networks based on application-dependent localized cloc k skew. The methodology is divided into four phases: 1) determination of an optimal clock skew schedule for improving circuit performance an d reliability; 2) design of the topology of the clock tree based on th e circuit hierarchy and minimum clock path delays; 3) design of circui t structures to implement the delay values associated with the branche s of the clock tree; and 4) design of the geometric layout of the cloc k distribution network. Algorithms to determine an optimal clock skew schedule, the optimal clock delay to each register, the network topolo gy, and the buffer circuit dimensions are presented. The clock distrib ution network is implemented at the circuit level in CMOS technology a nd a design strategy based on this technology is presented to implemen t the individual branch delays. The minimum number of inverters requir ed to implement the branch delays is determined, while preserving the polarity of the clock signal. The clock lines are transformed from dis tributed resistive-capacitive interconnect lines into purely capacitiv e interconnect lines by partitioning the RC interconnect lines with in verting repeaters. The inverters are specified by the geometric size o f the transistors, the slope of the ramp shaped input/output waveform, and the output load capacitance. The branch delay model integrates an inverter delay model with an interconnect delay model. Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clo ck skew between any two registers belonging to the same global data pa th are obtained as compared with SPICE Level-3.