SIMULATED ANNEALING APPROACH TO CROSSTALK MINIMIZATION IN GRIDDED CHANNEL ROUTING

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabri cation technology rapidly evolves. Accordingly, it becomes important t o minimize crosstalk caused by the coupling capacitance between adjace nt wires in the layout design for the fast and safe VLSI circuits. We present a simulated annealing approach based on segment rearrangement to crosstalk minimization in an initially gridded channel routing. The proposed technique is compared with previous track-oriented technique s, especially a track permutation technique whose performance is bound ed by an exhaustive track permutation algorithm. Experiments shelved t hat the presented technique is more effective than the track permutati on technique.