PLACEMENT AND ROUTING FOR PERFORMANCE-ORIENTED FPGA LAYOUT

Authors
ALEXANDER MJ COHOON JP GANLEY JL ROBINS G
Citation
Mj. Alexander et al., PLACEMENT AND ROUTING FOR PERFORMANCE-ORIENTED FPGA LAYOUT, VLSI design, 7(1), 1998, pp. 97-110
Citations number
43
Categorie Soggetti
Computer Science Hardware & Architecture","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
Journal title
VLSI design → ACNP
ISSN journal
1065514X
Volume
7
Issue
1
Year of publication
1998
Pages
97 - 110
Database
ISI
SICI code
1065-514X(1998)7:1<97:PARFPF>2.0.ZU;2-W
Abstract
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitio ning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathleng ths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel widt h required to place and route several benchmarks.