FUNCTIONALITY FAULT MODEL - A BASIS FOR TECHNOLOGY-SPECIFIC TEST-GENERATION

In this paper, we present the functionality fault model and demonstrat e its feasibility and advantages. In current designs, the fan-in of th e modules implemented in CMOS standard cell, mask programmable or fiel d-programmable gate array technologies rarely exceeds 4 on average. A functionality Fault model, based on the complete enumeration of the tr uth table of each logic module, is thus entirely feasible and enhances the quality of the test significantly. tests based on this model prov ide complete coverage of module behavior and interior faults as well a s input stuck-at and bridging faults of any multiplicity, reducing the need for technology and implementation-specific fault models. We have implemented the prototype software rest-etc and demonstrated its appl ication to generate high-quality test patterns. (C) 1998 Elsevier Scie nce Ltd. All rights reserved.