SMALL-SIGNAL GATE-TO-DRAIN CAPACITANCE OF MOSFET AS A DIAGNOSTIC-TOOLFOR HOT-CARRIER-INDUCED DEGRADATION

In this paper a method for the study of hot-carrier induced charge cen ters in MOSFETs based on a small-signal gate-to-drain capacitance meas urement is described. Numerical modeling and simulation is used to pro vide an understanding of the effects of spatially localized trapped ca rriers and interface states on this capacitance. Experimental gate-to- drain capacitance results are presented and compared with charge pumpi ng measurements. This method is used to investigate hot-carrier degrad ation of n- and p-channel MOSFETs after drain avalanche hot-carrier st ress conditions. It is concluded that under this stress condition the degradation of both n- and p-channel devices is due to the trapping of majority carriers and the generation of acceptor type interface state s in the top half of the silicon bandgap. (C) 1997 Elsevier Science Lt d.