A model describing how wearout leads to breakdown in thin silicon oxid
es has been developed. During wearout defects or traps are generated i
nside the oxide and at the oxide interfaces. The signature of the trap
generation is the permanent change in the transient current, in respo
nse to a voltage pulse, from an exponential decay to a 1/time decay. I
n oxides thinner than approximately 20 nm the dominant trap generation
mechanism appears to be determined by the high fields across the oxid
es and not electron flow through the oxides. Locally higher current de
nsities, flowing through the traps generated during wearout, lead to l
ocal breakdown. This model is critically dependent on the measurement
of the properties of the traps generated inside the oxides during the
wearout phase. The techniques for measurement of these traps and some
of their properties have been described. The ability of this model to
describe oxide charging, low-level leakages, transient currents, the r
ole of asperities, polarity dependences, and the fluence, time, thickn
ess, voltage and temperature dependences of oxide breakdown distributi
ons has been discussed. (C) 1997 Elsevier Science Ltd.