LDD DESIGN TRADEOFFS FOR SINGLE TRANSISTOR LATCH-UP AND HOT-CARRIER DEGRADATION CONTROL IN ACCUMULATION-MODE FD SOI MOSFETS

An experimental study has been conducted of the design tradeoffs of fu lly depleted (FD) accumulation mode Silicon-on-Insulator (SOI) MOSFET' s with regard to hot carrier reliability, single transistor latch-up a nd device performance, Three drain designs were considered, using Larg e-Tilt-Angle Implantation (LATID) for the LDD formation, Structures in corporating 0 degrees angle LDD implant, large angle LDD implant, and no LDD were fabricated, and their hot carrier reliability, single tran sistor latch-up voltage, and device performance in terms of drive curr ent and speed were determined, Correct interpretation of the experimen tal results was aided by performing PISCES numerical simulations, It w as found that the structure with the best hot carrier reliability (lar ge angle LDD implant) has the worst case latch-up voltage, and the one with the worst hot carrier reliability (no LDD implant) has the best latch-up voltage, Overall good device performance with acceptable hot carrier reliability and latch-up voltage is obtained with the 0 degree s angle LDD implant.