ANALYSIS OF EMITTER EFFICIENCY ENHANCEMENT INDUCED BY RESIDUAL-STRESSFOR IN-SITU PHOSPHORUS-DOPED POLYSILICON EMITTER TRANSISTORS

This paper analyzes the enhancement of emitter efficiency in in situ p hosphorus-doped polysilicon (IDP) emitter transistors, whose polysilic on emitter is crystallized from an in situ phosphorus doped amorphous Si film, There are two factors that enhance the emitter efficiency of the IDP emitter, One is a potential barrier at the IDP/substrate inter face produced by residual stress in the IDP layer, The other is a very thin oxide layer at the interface, which prevents epitaxial growth at the interface, We have distinguished between the emitter efficiency e nhancement due to each of these two factors by analyzing the character istics of three types of IDP emitter in which the residual stress and the thin oxide layer at the interface are controlled differently, We f ound that the potential barrier due to the residual stress increases t he emitter efficiency from about two times to about eight times depend ing on the emitter size, and that the thin oxide layer at the interfac e increases the emitter efficiency by about three times.