LOW OVERHEAD FAULT-TOLERANT FPGA SYSTEMS

Fault-tolerance is an important system metric for many operating envir onments, from automotive to space exploration. The conventional techni que for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testi ng, power consumption, volume, and weight. We have developed a new fau lt tolerance approach that capitalizes on the unique reconfiguration c apabilities of field programmable gate arrays (FPGA's). The physical d esign is partitioned into a set of tiles. In response to a component f ailure, a functionally equivalent tile that does not rely on the fault y component replaces the affected tile. Unlike application specific in tegrated circuit (ASIC) and microprocessor design methods, which resul t in fixed structures, this technique allows a single physical compone nt to provide redundant backup for several types of components. Experi mental results conducted on a subset of the MCNC benchmarks demonstrat e a high level of reliability with low timing and hardware overhead.