A RATED-CLOCK TEST METHOD FOR PATH DELAY FAULTS

Current test generation algorithms for path delay faults assume a vari able-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan s equential circuit testing is impractical. A rated-clock path delay sim ulator shows a large drop in coverage for vectors obtained from existi ng test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test applicati on. In this algorithm, signals are represented for three-vector sequen ces. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward ju stification, we derive an optimal 41-valued algebra, This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths.