CONCURRENT FAULT SIMULATION ON MESSAGE-PASSING MULTICOMPUTERS

Even though hardware accelerators are common in very large scale integ ration (VLSI) computer-aided design (CAD), fault simulation is a notab le exception because of limited availability of memory, the need for d ynamic memory management and the complexity of the algorithms themselv es. Although simplified fault simulation algorithms that assume a zero delay circuit model can be accelerated, their applicability is limite d. Most application specific integrated circuits (ASIC's) designed in industry today have on chip memory blocks of different dimensions and characteristics, enhancing the complexity of a fault simulator. In thi s paper, we present a multiple delay algorithm for concurrent fault si mulation of logic gates and functional memory blocks. This algorithm h as been implemented on the microprogrammable accelerator for Rapid sim ulation (MARS) hardware accelerator system with a 22 MHz clock and a c apacity to simulate circuits with millions of devices. Speedup factors of 20 to 30 are easily achieved when compared to software simulators running on comparable hardware platforms and using identical circuit m odels.