EVALUATION OF PLASMA CHARGING DAMAGE DURING POLYSILICON GATE ETCHING PROCESS IN A DECOUPLED PLASMA SOURCE REACTOR

Charging induced damage of thin gate dielectric during polysilicon gat e etching in a high density decoupled plasma source was investigated f or 0.16 and 0.24 mu m gates on 30 Angstrom nitrided gate oxide. The un doped polysilicon gates were etched with a HBr/He/O-2 based process re cipe. The optimized process recipe resulted in vertical profiles (89 d egrees-90 degrees) with microloading of <1 degrees. No notching oi the polysilicon or punch through of the thin gate oxide was observed. Gat e leakage and breakdown voltage measurements after gate formation were made on metal-oxide-semiconductor capacitor structures with antenna r atios ranging from 100:1 to 1000:1. These measurements did not exhibit any damage to the thin gate dielectric. In addition, no significant c hange in the damage characteristics was observed over a wide process w indow around the optimized recipe, i.e., increased over etch (OE) time , increased source power, or reduced bias power in the OE step. A soft landing scheme was used for the etching of poly gates. This scheme pr ovides vertical profiles without punch through and with minimum damage to the thin gate oxide and the substrate. (C) 1998 American Vacuum So ciety.