SCOAP-BASED TESTABILITY ANALYSIS FROM HIERARCHICAL NETLISTS

Circuits of VLSI complexity are designed using modules such as adders, multipliers, register files, memories, multiplexers, and busses, Duri ng the high-level design of such a circuit, it is important to be able to consider several alternative designs and compare them on counts of area, performance, and testability. While tools exist for area and de lay estimation of module-level circuits, most of the testability analy sis tools work on gate-level descriptions of the circuit. Thus an expe nsive operation of flattening the circuit becomes necessary to carry o ut testability analysis. In this paper, we describe a time and space-e fficient technique for evaluating the well known SCOAP testability mea sure of a circuit from its hierarchical description with tyro or more levels of hierarchy. We introduce the notion of SCOAP Expression Diagr ams for functional modules, which can be precomputed and stored as par t of the module data base. Our hierarchical testability analysis progr am, HISCOAP, reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a systematic manner . The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. We show that our algorithm also has a straightforward para llel realization.