CHARACTERIZATION OF CATASTROPHIC FAULTS IN RECONFIGURABLE SYSTOLIC ARRAYS

A common technique widely used to achieve fault tolerance in systolic arrays consists in incorporating in the array additional processing el ements (PEs) and extra bypass links. Given a sufficient number of PEs and a large enough set of bypass links, it might seem that the array c an easily tolerate a large number of faults provided they do not occur in consecutive locations. It is not always the case as shown in this paper. In fact, certain fault patterns exist and may occur which would prevent any kind of restructuring of the aray, thus making the struct ure unusable. For a given set of bypass links from each PE in the arra y, it is possible to identify such fault patterns which will prevent a ny reconfiguration. In this paper, we identify the class of fault patt erns that are catastrophic for linear systolic arrays, examine their c haracteristics, and describe a method for constructing such fault patt erns.