ON SELF-CHECKING DESIGN OF CMOS CIRCUITS FOR MULTIPLE FAULTS

A technique for designing totally self-checking (TSC) FCMOS (Fully Com plementary MOS) designs for multiple faults is presented in this paper . The existing techniques for self checking design consider only singl e faults, and suffer from high silicon area overhead. The multiple fau lts considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS de sign, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experimental results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS ci rcuits.