THRESHOLD VOLTAGE AND CHARGE CONTROL CONSIDERATIONS IN DOUBLE-QUANTUM-WELL SI SI1-XGEX P-TYPE MOSFETS/

A double quantum well Si/Si1-xGex p-channel MOSFET (DQW-PMOS) is propo sed and analyzed. Different Si/Si1 - xGex DQW designs both on bulk sil icon and on silicon-on-insulator (SOI) substrates have been investigat ed using analytical and numerical approaches. Analytical modeling was used to investigate the threshold voltage of different channels. The n umerical approach focused on the self-consistent 2D solution of the Sc hrodinger and Poisson equations to determine the confined hole density profile at different gate potentials. Both approaches reach the same conclusion regarding the best Si/Si-1 Ge-- x(x) DQW-PMOS design with r espect to gate charge control and threshold voltage considerations. Am ong the investigated designs, the best hole confinement profile was fo r a structure with a 30%-Ge-content well at the substrate end (channel 1) and a 15%-Ge well close to the gate oxide (channel 2). Most of the confined holes in this structure are attributed to carriers from chan nel i. For this design, the hole concentration profile in channel 1 wa s found to have a peak at the center of the channel. This retrograded DQW structure benefits from minimizing the mobility degradation due to interface scattering at the top Si/Si1 - xGex heterojunction. Therefo re, the proposed structure of the DQW here shows that the built-in pot ential of the composite Si spacer layer and the top QW helps in the op timization of the hole distribution in the bottom QW. In addition, the above design offers better charge control compared to a structure wit h a 15%-Ge well at the substrate end and a 30%-Ge well close to the ga te oxide. The implementation of the former structure leads to less 1/f -noise and random telegraph signals. Hence, the structure is suitable for future analog applications. (C) 1998 Elsevier Science Ltd. All rig hts reserved.