INTERCONNECTION CAPACITANCE MODELS FOR VLSI CIRCUITS

A new set of capacitance models is developed for delay estimation of V LSI interconnections. The set of models is derived for five representa tive wiring structures, with their combinations covering arbitrary VLS I layouts. A semi-empirical approach is adopted to deal with complicat ed geometry nature in VLSI and to allow for closed-form capacitance fo rmulas to be developed to provide direct observation of capacitance va riation vs process parameters as well as computational efficiency for circuit simulation. The formulas are given explicitly in terms of wire width, wire thickness, dielectric thickness and inter-wire spacing. T he models show good agreement with numerical solutions from RAPHAEL an d measurement data of fabricated capacitance test structures. The mode ls are further applied and validated on a ring oscillator. It is shown that the frequency of the ring oscillator obtained from HSPICE simula tion with our models agrees well with the bench measurement. (C) 1998 Published by Elsevier Science Ltd. All rights reserved.