AREA-TIME-EFFICIENT VLSI RESIDUE-TO-BINARY CONVERTERS

The authors present highly area-time-efficient VLSI implementations of residue reverse converters called compressed multiply accumulate (CMA C) converters. This efficiency results from carefully identifying and eliminating redundancy in existing proposals. Specifically, the partia l sum generation and addition are merged into a single carry-save addi tion operation. Also, module multipliers are replaced by simple adders by the bit unfolding and uncorrected residues technique. The CMAC rev erse converters proposed here were fabricated in a 0.8 mu m N-well CMO S process. Due to the techniques mentioned, the resulting VLSI impleme ntation was 3-4 times smaller than recently reported results, while de livering identical throughput and achieving four times lower delay. Th e AT(2) efficiency of these converters O(n(2)log(3)n) equals the best known to date. Comprehensive analysis of the various implementation op tions (CPA, CLA or serial) presented will be of great value to the VLS I system designer in choosing a reverse converter that conforms to the delay, area and power requirements imposed by a given application.