SILC-RELATED EFFECTS IN FLASH (EPROM)-P-2S - PART I - A QUANTITATIVE MODEL FOR STEADY-STATE SILC

In this paper a quantitative model. for the steady-state component of the stress induced leakage current (SILC) is developed [1], The establ ished model is based on the observation of basic degradation monitors on conventional, thermal SiO2 gate dielectrics in the thickness range of 6.8-7.1 nm, From a systematic, experimental study, it has been foun d for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection pol arity), can be uniquely described by a simple, semi-empirical relation , which consists of two parts: 1) the dependence on the measurement fi eld is described as Fowler-Nordheim (FN) tunneling through an oxide ba rrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bul k oxide traps. Except for a calibration, depending on the oxide thickn ess and processing, no model parameters have to be adjusted in order t o describe all our data. Also, based on bake experiments it has been c oncluded that interface traps are not causally related to the steady-s tate SILC in spite of the linear relation which exists between both. F urthermore, these bake experiments provide new evidence that bulk oxid e traps play a crucial role in the SILC conduction mechanism.