SILC-RELATED EFFECTS IN FLASH (EPROM)-P-2S - PART II - PREDICTION OF STEADY-STATE SILC-RELATED DISTURB CHARACTERISTICS

In this paper, a new methodology is developed, and applied thereafter, to predict the disturb characteristics of an arbitrary Flash (EPROM)- P-2 device which are related to steady-state stress induced leakage cu rrent (SILC) [1], This prediction methodology is based on a quantitati ve model for steady-state SILC, which has been developed on capacitors and nFET's as was reported earlier in Part I, Here, this model is sho wn to be also valid for tunnel oxide Flash (EPROM)-P-2 devices, and us ed thereafter in a consistent and well-understood cell optimization pr ocedure. The model requires as only input basic cell parameters and an oxide qualification obtained at the capacitor and transistor level.