LOW-FIELD BULK DEFECT GENERATION DURING UNIFORM CARRIER INJECTION INTO THE GATE INSULATOR OF INSULATED GATE FIELD-EFFECT TRANSISTORS AT VARIOUS TEMPERATURES

Low-field electron injection of up to 10(19) e/cm(2) across the Si-SiO 2 interface into the gate insulator of an n-channel insulated gate fie ld effect transistor using an optically assisted hot electron injectio n technique was conducted from room temperature down to 100K. It was f ound that the room temperature data could be modeled quite accurately by attributing all of the observed Delta V-t to generation of negative ly charged defects whose generation follows a power law. At reduced te mperatures, ''structure'' in the observed data indicated the presence of one shallow first order trap. In this case, a combination of a powe r law generation term and a single first order trap cross section was used, and is needed, to accurately model the data. It was also found t hat trap generation is enhanced significantly as the temperature is re duced. Threshold voltage shifts were shown by charge pumping measureme nts not to be associated with interface state generation under the low -field conditions employed. The results presented here indicate that e ven at very low applied oxide fields (1 MV/cm) hot electron injection not only results in the filling of existing traps, but also in the gen eration of new charged bulk defects whose generation rate increases as the temperature is reduced, or the injection current density is incre ased. These results also raise questions about some of the reports of small cross section trapping centers less than or equal to 10(-17) cm( 2), since these were typically characterized by applying a only first order trapping model to high field and/or high current density injecti on data. Such aggressive injection conditions could very easily have r esulted in the generation of charged bulk defects which could then be erroneously identified as one or more small cross section traps.