A SPICE COMPATIBLE SUBCIRCUIT MODEL FOR LATERAL BIPOLAR-TRANSISTORS IN A CMOS PROCESS

This paper describes a SPICE compatible subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 mu m CMOS process. The e xtraction of a de parameter set for the lateral device is more complic ated than for a vertical device because of the presence of two parasit ic vertical bipolar transistors which are formed by the emitter/collec tor, the base and the substrate regions, The SPICE Gummel-Poon model d oes not predict the substrate current accurately. This paper proposes a method which involves the use of a subcircuit incorporating three SP ICE Gummel-Poon models [representing one lateral and two parasitic ver tical bipolar junction transistors (BJT's)]. The development of this m odel, its implementation and the results obtained are outlined and dis cussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured de data including substrate current prediction.