IMPROVED OUTPUT ESD PROTECTION BY DYNAMIC GATE FLOATING DESIGN

Authors
CHANG HH KER MD
Citation
Hh. Chang et Md. Ker, IMPROVED OUTPUT ESD PROTECTION BY DYNAMIC GATE FLOATING DESIGN, I.E.E.E. transactions on electron devices, 45(9), 1998, pp. 2076-2078
Citations number
13
Categorie Soggetti
Engineering, Eletrical & Electronic","Physics, Applied
Journal title
I.E.E.E. transactions on electron devices → ACNP
ISSN journal
00189383
Volume
45
Issue
9
Year of publication
1998
Pages
2076 - 2078
Database
ISI
SICI code
0018-9383(1998)45:9<2076:IOEPBD>2.0.ZU;2-W
Abstract
A dynamic gate Boating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this no vel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-mu m CMOS process.