MESH ROUTING TOPOLOGIES FOR MULTI-FPGA SYSTEMS

There is currently great interest in using fixed arrays of FPGA's for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGA's. This topology can have a great effect on the area and delay of the resulting system. Cr ossbar, Hierarchical Crossbar, and Mesh interconnection schemes have a ll been proposed for use in FPGA-based systems. In this paper, we exam ine Mesh interconnection schemes, and propose several constructs for m ore efficient topologies. These reduce interchip delays by more than 6 0% over the basic four-way Mesh.