A HIGH-LEVEL SYNTHESIS SYSTEM FOR VLSI IMAGE-PROCESSING APPLICATIONS

We present a VLSI synthesis environment dedicated to the design of ima ge processing architectures. The environment includes a ''front-end'' data-flow emulator for validation of the algorithms and the RTL-synthe sis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the ''re stricted'' domain of concerned applications. Two simulated Annealing ( SA) algorithms run in sequence for data-path synthesis (scheduling and module selection) and then for control synthesis and data-path comple tion (binding). An interesting feature of the first optimization is th e use of the data-flow graph regularity to predict the control influen ce in terms of the future design. A few designs have already been comp iled under this environment including a default detector presented her e.