ESD PROTECTION METHODOLOGY FOR DEEP-SUBMICRON CMOS

Electrostatic discharge is considered to be a serious treat of integra ted CMOS circuits since the feature size reached about 1.5-1.0 mu m. S ince then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological l imitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward a daptive conservative methodology is step by step replaced by a methodo logy considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is c oncluded that the scaling based limitations might grow to a significan t problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular i f the high-frequency properties of such technologies should not be aff ected (C) 1998 Elsevier Science Ltd. All rights reserved.