MODELING AND SIMULATION OF HOT-CARRIERS DEGRADATION OF HIGH-VOLTAGE FLOATING LATERAL NDMOS TRANSISTORS

This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simula tion has been done in order to understand the degradation phenomena ba sed on bulk current. Two points of high Impact Ionization rates have b een found : one close to the channel junction but in depth, and the se cond one in the drift region. This later explains the Hot Carrier Degr adation of the R-on parameter observed experimentally. (C) 1998 Elsevi er Science Ltd. All rights reserved.