GATE BIAS STRESS IN HYDROGENATED AND UNHYDROGENATED POLYSILICON THIN-FILM TRANSISTORS

Polysilicon Thin Film Transistors (TFT's), fabricated at temperature l ower than 600 degrees C, are now largely used in many applications, pa rticularly in large area electronics. The reliability of these TFT's u nder different electrical conditions is then questionable. In this wor k, Gate bias stress is studied in two types of polysilicon TFT's origi nated from the same process. One type is unhydrogenated and the other is submitted to a Radio-Frequency hydrogen plasma. A's this hydrogenat ion step is known to improve the TET's performances but to introduce u nstability, the unhydrogenated TFT's are expected to be more stable. T he behaviours of the two types of TFT's under the gate bias stress are found however only different. The bias aging of unhydrogenated TET's fit with the known model of the n-channel c-Si MOSFET's bias stress. T he behaviour of the hydrogenated TFT's is explained from the model of defect creation in hydrogenated amorphous silicon. (C) 1998 Elsevier S cience Ltd. All rights reserved.