Az. Wang et al., A STUDY OF NMOS BEHAVIOR UNDER ESD STRESS - SIMULATION AND CHARACTERIZATION, Microelectronics and reliability, 38(6-8), 1998, pp. 1183-1186
A full-scale simulation-aided ESD design methodology was used to desig
n a group of NMOS ESD protection units. Silicon results match the simu
lation data quite well. Both simulation and measurement data show good
ESD performance uniformity across NMOS poly finger length and finger
number in ladder structures in a large range. Optimal layout pattern f
or ladder structures was obtained with the aid of simulation. (C) 1998
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