A STUDY OF NMOS BEHAVIOR UNDER ESD STRESS - SIMULATION AND CHARACTERIZATION

Authors
WANG AZ TSAY C LELE A DEANE P
Citation
Az. Wang et al., A STUDY OF NMOS BEHAVIOR UNDER ESD STRESS - SIMULATION AND CHARACTERIZATION, Microelectronics and reliability, 38(6-8), 1998, pp. 1183-1186
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Microelectronics and reliability → ACNP
ISSN journal
00262714
Volume
38
Issue
6-8
Year of publication
1998
Pages
1183 - 1186
Database
ISI
SICI code
0026-2714(1998)38:6-8<1183:ASONBU>2.0.ZU;2-P
Abstract
A full-scale simulation-aided ESD design methodology was used to desig n a group of NMOS ESD protection units. Silicon results match the simu lation data quite well. Both simulation and measurement data show good ESD performance uniformity across NMOS poly finger length and finger number in ladder structures in a large range. Optimal layout pattern f or ladder structures was obtained with the aid of simulation. (C) 1998 Elsevier Science Ltd. All rights reserved.