HIGH-DENSITY, INDUCTIVELY-COUPLED PLASMA ETCH OF SUB HALF-MICRON CRITICAL LAYERS - TRANSISTOR POLYSILICON GATE DEFINITION AND CONTACT FORMATION

Sub-half-micron device design rules require precise control over two c ritical etch layers: transistor polysilicon gate definition and contac t formation. The definition of the transistor polysilicon gate electro de is essential to the performance of the device. In addition, the sma ll geometries and thin underlying gate oxide demand a high level of co ntrol over the gate dimensions. The design rules also require the form ation of high-aspect-ratio contacts and vias with nearly vertical side walls and minimal critical dimension variation. To define these featur es, a deep-ultraviolet photolithography process was developed, incorpo rating a bottom antireflective coating (ARC). The etch processes used to translate these features into polysilicon (gates) and oxide (contac ts) required an in situ ARC dry-develop step and a fast etch rate for high throughput with good uniformity while maintaining a high selectiv ity to any underlying layers. To achieve these stringent requirements, low-pressure, high-density-plasma reactors with independent substrate bias power control were needed. (C) 1998 American Vacuum Society.