FEASIBILITY OF GATE PATTERNING BY USING A HARD MASK ON 0.25 MU-M TECHNOLOGY AND BELOW

In this article, the, feasibility of gate patterning for 0.25 mu m tec hnology and below by using a hard. mask has been investigated in terms of polymerization, selectivity to the gate oxide, compatibility with deep ultraviolet lithography, and plasma damage. A 50 nm SiO2 hard mas k is thick enough to protect the underlying polysilicon layer without profile distortion at the outermost lines. The use of a SiO2 hard mask also increases the gate oxide selectivity up to 45% as compared to a photoresist mask. The amount of carbon atoms in the etched gate oxide area is much lower for the SiO2 mask process than for the photoresist process. Carbon plays an important role in reducing the gate oxide sel ectivity and decreasing the oxide reliability. Due to local charging, oxide pitting along the polysilicon lines is much more pronounced when using a photoresist mask, Charging effects caused by electron shading were expected to be lower for the thin SiO2 mask due to the lower asp ect ratio; however, from Qbd (charge to 'breakdown) measurements on ov erlapping capacitors, no significant difference between the SiO2 and t he photoresist mask processes was observed. In the mean time, the 4.5 nm gate oxide was better than the 7 nm gate oxide in terms of oxide de gradation by charging. In the regime of gate oxide thickness under 5 n m, physical damage by charging seems to be more of a concern than elec trical damage. Consequently, a SiO2 hard mask process can provide clea n, highly selective, and less damaged polysilicon gate patterning for 0.25 mu m technology and below. (C) 1998 American Vacuum Society. [S07 34-211X(98)05505-X].