A NEW APPROACH TO SIMULATING N-MOSFET GATE CURRENT DEGRADATION BY INCLUDING HOT-ELECTRON-INDUCED OXIDE DAMAGE

A new gate current model which considers the hot-electron induced oxid e damage in n-MOSFET's was developed for the first time. The spatial d istributions of oxide damage, including the interface state (N-it) and oxide trapped charge (Q(ox)), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N-it and Q(ox) has thus been proposed, Furthermore, the indi vidual contributions of N-it and Q(ox) to the degradation of gate curr ent can thus be calculated separately using these oxide damage. For de vices stressed under maximum gate current biases, it was found that th e interface state will degrade the gate current more seriously than th at of the oxide trapped charge. In other words, the interface states w ill dominate the gate current degradation under I-G (max). Good agreem ent of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monito r that is superior to substrate current for submicron device reliabili ty applications, in particular for EPROM and Flash EEPROM devices.