THE EFFECTS OF INTERLAYER DIELECTRIC DEPOSITION AND PROCESSING ON THERELIABILITY OF N-CHANNEL TRANSISTORS

We report on the effects of interlayer dielectric (ILD) deposition and processing on metaloxide-silicon field-effect transistor's (MOSFETs) Fowler-Nordheim (FN) stress reliability. The ILD materials examined ar e plasma-enhanced chemical vapor deposited (PECVD) fluorinated silicon oxide (FSO), PECVD tetra-ethyl-ortho-silicate (TEOS), and spin-on pol ymer. We used n-MOSFETs with 0.35 mu m channel lengths and 90-Angstrom -thick gate oxides as our test Vehicles and transistor reliability was assessed using transistor parameter, charge-to-breakdown, and charge pumping measurements. We found out that deposition and processing of t he polymer ILD have the least damaging effects on transistor's reliabi lity, whereas deposition and processing of the FSO ILD cause the highe st device degradation. We also examined the synergy between damage fro m ILD deposition and processing and damage from plasma etching by meas uring a special test module containing transistors with charging anten nae that are sensitive to gate-definition plasma etching. We observed that damage from plasma etching dominates over damage from polymer and TEOS ILD deposition and processing as indicated by the direct correla tion between FN reliability and the antenna ratio. However, this was o bserved not to be the case for damage from FSO ILD deposition and proc essing which was observed to be as effective as plasma etching damage and to give rise to a ''reverse antenna'' effect; i.e., the smaller th e antenna the less reliable the MOSFET. This is attributed to an inter action which involves plasma charging, fluorine diffusion and defect p assivation by fluorine. (C) 1998 Published by Elsevier Science Ltd. Al l rights reserved.