BUILDING IN RELIABILITY WITH LATCH-UP, ESD AND HOT-CARRIER EFFECTS ON0.25 MU-M CMOS TECHNOLOGY

In this study, three major reliability aspects, hot carrier effects, l atch-up and electrostatic discharge (ESD) have been simultaneously stu died on a 0.25 mu m complementary metal-oxide silicon (CMOS) technolog y. For this purpose, three source-drain architectures large angle tilt ed implementation drain (LATID, MDD, Abrupt) processed on different ki nds of substrate (bulk and epitaxial ones) are compared with respect t o these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source-drain architecture affect s, of course, the hot carrier reliability but also the ESD performance s. A thinner epitaxial substrate is effective in reducing latch-up occ urrences, but degrades the ESD failure threshold. Consequently, global technology optimisation will be a trade off between these various rel iability aspects. (C) 1998 Elsevier Science Ltd. All rights reserved.